Timing circuits take on a broad range of forms and implementations, with their variety stemming from the sheer range of applications in which timing functions are required. High-resolution timing or precise frequency control applications in particular impose special design challenges, and may tax available circuit technologies when pushed beyond a given level of timing precision.
Oftentimes, the design challenge extends beyond constructing a timing circuit capable of high-resolution timing into the design of test circuits capable of characterizing and verifying performance and accuracy of the timing circuit at hand. If the timing circuit of interest is meant to measure small increments of time, say, for example, billionths or even trillionths of a second, verifying its operation poses decidedly non-trivial challenges. Factoring in the economic constraints placed on all but the most esoteric products only exacerbates the design problem.
One particular type of timing circuit is based on a digital delay line. A delay line generally comprises a circuit device that imparts a fixed or sometimes variable delay to an input waveform. Thus, a signal transition in an input waveform manifests itself on the delay line output some desired delay interval later in time.
Delay line based timing applications exploit a particular delay line implementation, in which the delay function between input and output is realized by successively connecting a chain of digital gates, each one having a characteristic delay interval, which may be the intrinsic propagation delay of the gate itself. Thus, a signal transition input to the delay line sequentially shifts or propagates through the series of interconnected gates. Each gate or delay stage is offset in time from the beginning of the delay line based on the accumulated delay between it and the first delay stage in the chain.
Each delay stage may be tapped, i.e., the stage output signal may be brought out. A propagating signal transition appears sequentially on these taps at time intervals determined by the delay interval of the corresponding delay stages. Thus, the tap signals correspond to sequential time offsets relative to the beginning of the delay line, and may be used to time certain events with a timing precision that is fundamentally limited only by the lower limits on delay stage propagation delay.
Because the time measurement precision of a delay line may approach the intrinsic propagation delay of a single electronic gate or like logic element, verifying that one or more of the delay stages meet desired time interval requirements poses significant challenges. However, in many applications where confirmation of timing accuracy is required or desirable, such as in safety critical applications, it is nonetheless necessary to devise a measurement and verification system capable of testing the timing of delay stages within a delay line.
Preferably, such a test system is flexible enough to accommodate testing over a range of required time resolutions. Further, the test system should be reliable, accurate, and inexpensive enough to include as part of the timing device that incorporates the delay line timing circuit. In this manner, the test circuit may be included within the device, thereby allowing the overall system to calibrate and self-test its delay line circuit or circuits.
The present invention is an apparatus and method for calibrating and testing a digital delay line formed as a sequence of delay stages. A timing circuit generates a test signal that shifts in time with a precise and stable relationship to a reference signal. Sampling the test signal at time intervals based on the successive delay stages comprising the delay line in synchronization with the reference signal reveals whether individual delay stages in the delay line impart the expected or required delay intervals. Thus, the timing circuit may be used to characterize actual delay line, with the characterization information used as, for example, delay line calibration data.
Preferably, the test and reference signals are generated based on controlling a frequency offset between two frequency generators, which may be implemented as precision oscillators. A phase lock loop (PLL) or other control circuit maintains a constant frequency difference between the two oscillators. One of the two oscillators is set at a desired frequency, and the control circuit offsets the frequency of the second oscillator by the desired frequency difference.
As phase is the integral of frequency, maintaining the two oscillators at a constant frequency difference forces the two oscillator output signals to have a linearly changing phase offset, which repeatedly cycles through 360 degrees of phase offset at a rate determined by the difference frequency. Because phase shift in the frequency domain translates into time offset in the time domain, the linearly changing phase relationship causes one of the oscillator signals to shift in time relative to the other signal. The magnitude of the frequency difference between the two oscillators determines the relative time shift between the reference and test signals per cycle.
Thus, by setting the frequency difference appropriately, the second oscillator signal may be made to shift a very slight and precisely controlled amount with each cycle of the first oscillator signal. This time shift may, within the control limits of the oscillators and control circuit, be made arbitrarily small. More particularly, the resolution of the time shift depends on the ability to maintain a slight frequency difference between two oscillators, rather than depending on logic circuits operating at speeds high enough to generate time increments small enough for verifying the already tight timing of the delay line.
Dividing the frequency of the first oscillator signal to create the reference signal provides a slower signal that may be used for synchronizing the start of the delay line to the test signal. Because the reference signal is derived from the first oscillator, the relative phase of the test signal changes with each cycle of the reference signal. In this manner, the test signal shifts through a plurality of time offsets relative to the beginning time of the delay line over repeated cycles of the reference signal.
Each delay stage of the delay line represents a delay interval or time bin, with the overall delay line representing a time window. By tracking the phase offset between the oscillator signals, a test protocol may be devised that runs for a determined number of reference signal cycles, such that a test signal edge is distributed at known time intervals across the time window represented by the delay line. The test signal is recorded or sampled at discrete sample points at sample times determined by the delay stages in the delay line for each cycle of the reference signal.
Because the distribution interval of test signal edges across the time window is known, the controlling system may determine the approximate width of the time bins represented by the delay stages by counting the number of test signal edges that fall within each bin. If the time interval between accumulated test signal edges is small in comparison to the nominal or expected width the delay stage time bins, the width of the bins may be estimated with good accuracy. The time interval between the accumulated test signal edges is a function of test signal frequency relative to the difference frequency between the first and second oscillators, and the resolution with which the phase offset between the two oscillator signals is tracked.
Phase tracking may use a phase clock, which may be a digital counter with a count resolution chosen to provide the desired test signal edge interval. The phase counter clock is preferably derived from the same oscillator signal used to derive the reference signal. If the phase counter is configured with the proper count modulus or rollover value with respect to the reference signal, it may be incremented a fixed number of counts per reference signal, while still hitting every possible count value over a number of rollover cycles. This allows the reference signal, which drives test signal sampling, to cycle at a lower rate than the phase clocking rate, which may be advantageous in terms of lessening system-processing overhead.